The invention relates generally to the transfer of data using asynchronously timed signals and, more particularly, to a system and method that permits data from an external asynchronously timed system to be infinitely delayed with respect to internal timing.
Communication between systems necessarily involves a controlled transfer of data. Even when communicating networks use the same protocols, the two network clocks must be synched to each other, or other control signals must be used to latch the data from one network to the other. In packet data communications, such as the communication protocols used in the transfer of data across the Internet, timing is an issue in the receiver and transmitter interfaces to network interface processors.
One conventional method for latching parallel data between a first system having an external timing domain, for example a controller or framer, to a second system with an internal timing domain, such as a transmitter, has been in the implementation of propagation delay constraints. These constraints are relatively easy to abide by at low rate rates, but become more difficult to meet as the byte frequency, or rate of data transfer increases. One possible constraint is a specified maximum delay of the byte clock as it comes out of the transmit device, passes through the interface device, and returns to the transmit device. This delay needs to be less than one byte time, which is not feasible at high rates of data transfer.
An alternative method is to route the outgoing byte clock directly to the incoming byte clock of the transmit device and control the propagation delay of the byte clock to the incoming parallel data. This maximum delay also becomes difficult to meet as the byte frequency increases.
The third method is called forward clocking, in which the incoming byte clock is tied to the reference clock input. This establishes a relationship between the internal and external timing domains since the voltage controlled oscillator (VCO) locks to the reference clock. The problem with this method is that the byte clock is not a clean enough source to be used as a VCO reference clock when SONET jitter requirements need to be met.
It would be advantageous to have a method for using the clock of a first system to write data to a second system, and to use the clock of the second system to read the data from the second system.
It would be advantageous if the clock of the first system could be infinitely delayed with respect to the clock of the second system.
It would be advantageous if data could be latched through the second system as long as the clock drift between the two system clocks remained relatively constant.
It would be advantageous if the latching of data from the first system to the second system could be automatically reinitialized when the drift between the two system clocks became large enough that a danger existed of overwriting data.
Accordingly, a system is provided for transferring asynchronously timed data. The system comprises a phase error circuit to receive a first clock signal with a first frequency, and a second clock signal at the same frequency. The phase error circuit measures a phase offset between the first and second clock signals, and provides a phase error signal when a phase offset drift exceeds a specified maximum drift. The system also comprises a data transfer circuit to write and read incoming data. The data transfer circuit writes data with the second clock signal and reads the data at the first clock signal when the phase offset between the first and second clock signals is within the specified phase drift tolerance. The data transfer circuit supplies the first and second clock signals to the phase error circuit for measurement.
Typically, the data to be written is supplied by an interface circuit with a PICLK clock signal. A clock generator provides a PCLK clock signal. The first clock signal is derived from the PCLK clock signal and the second clock signal is derived from the PICLK clock signal. In some aspects of the invention the PICLK is asynchronously derived from the PCLK.
The data transfer circuit includes N banks of registers, with each register having an input to write data from the interface circuit, and an output to provide read data that is transferred. The data to be written is fanned out to the N register inputs. Then, the data is demultiplexed into the N register inputs and shifted through each register to the output using the second clock signal. An N:1 multiplexer (MUX) circuit has N data inputs connected to the corresponding register outputs, and N select inputs to receive first clock signals. The MUX multiplexes the data to be read from the N register outputs in response to the first clock signals.
A method for transferring data between asynchronously timed systems is also provided. The method comprising:
generating a first clock having first frequency;
generating a second clock at the first frequency having a first redetermined phase offset with respect to the first clock;
writing data with the second clock to a bank of N registers; and reading data from the bank of N registers with the first clock;
measuring phase offset between the first and second clocks to determine if the phase offset has drifted out of tolerance from the first phase offset by referencing a second clock edge with to a corresponding first clock edge; and
in response to measuring the phase offset drifting out of tolerance from the first phase offset, reinitializing the generation of the first and second clocks to reestablish the first phase offset.